Semiconductor Design Engineer H-1B salary at Micron Technology — 73 certified filings (FY2022–FY2026)
- 28
- Filings · FY2025
- $119k
- Median base · FY2025
- $108k–$136k
- Middle 50% · FY2025
- ±0%
- vs market median · all years
Micron Technology filed 28 certified H-1B LCAs for Semiconductor Design Engineer in FY2025, with a median base salary of $119k and the middle 50% of offers between $108k and $136k. Across all years its $119k median is in line with the $119k market median for Semiconductor Design Engineer. It has filed 73 Semiconductor Design Engineer LCAs since FY2022, most often in Boise, ID.
How much does Micron Technology pay a Semiconductor Design Engineer?
Certified base salary for Semiconductor Design Engineer at Micron Technology by fiscal year: each box is the p25–p75 range, the heavy line the median, the whiskers reach p10–p90. $119k median in FY2025. Base pay only — hover a year for its figures.
Does Micron Technology pay Semiconductor Design Engineers above the market?
Micron Technology's all-years median against every employer's certified Semiconductor Design Engineer LCAs — in line with the market. Same cleaned DOL title, same base-salary definition, so the two rows compare like for like.
| Base salary for this title | Filings | Median |
|---|---|---|
| Micron Technology | 73 | $119k |
| All employers · Semiconductor Design Engineer | 90 | $119k |
How has Micron Technology's Semiconductor Design Engineer hiring changed by year?
12 certified Semiconductor Design Engineer filings in FY2022 → 18 in FY2026. The change column is each year against the one before.
| Fiscal year | Filings | vs prior FY | Median base |
|---|---|---|---|
| FY2026 | 18 | −36% | $119k |
| FY2025 | 28 | +155% | $119k |
| FY2024 | 11 | +175% | $110k |
| FY2023 | 4 | −67% | $96k |
| FY2022 | 12 | — | $117k |
Which wage levels does Micron Technology file for Semiconductor Design Engineer?
DOL prevailing-wage levels I–IV approximate experience tiers (I = entry, IV = fully competent). 29% of Micron Technology's Semiconductor Design Engineer filings sit at Level III–IV. Higher levels earn more entries in the wage-weighted H-1B lottery.
Share of 69 Semiconductor Design Engineer filings with a wage level · all years
- Level I8.7%6
- Level II62.3%43
- Level III20.3%14
- Level IV8.7%6
Where does Micron Technology hire H-1B Semiconductor Design Engineers?
Worksite states and cities on the certified filings for this title, all years, with the median base salary at each.
| State | Filings | Median base |
|---|---|---|
| Idaho | 35 | $109k |
| Texas | 17 | $123k |
| California | 11 | $137k |
| Georgia | 10 | $112k |
| City | Filings | Median base |
|---|---|---|
| Boise, ID | 35 | $109k |
| Richardson, TX | 15 | $128k |
| Atlanta, GA | 10 | $112k |
| San Jose, CA | 9 | $137k |
| Allen, TX | 2 | $115k |
| Folsom, CA | 2 | $121k |
Also filed as
Micron Technology's other sponsored titles, and the employers that file the most Semiconductor Design Engineer LCAs. All years.
Other titles at Micron Technology
| Job title | Filings | Median base |
|---|---|---|
| Design Engineer | 79 | $115k |
| Process Engineer | 57 | $93k |
| Supply Chain Engineer | 54 | $85k |
| IT Software Engineer | 52 | $90k |
| Semiconductor Process Engineer | 52 | $109k |
| Equipment Engineer | 48 | $98k |
| Senior Design Engineer | 44 | $135k |
| Firmware Engineer | 41 | $120k |
| Data Scientist | 39 | $107k |
| Industrial Engineer | 35 | $83k |
Top Semiconductor Design Engineer sponsors
| Employer | Filings | Median base |
|---|---|---|
| Teradyne | 14 | $125k |
| Sankalp Usa | 2 | $79k |
| Analog Devices | 1 | $104k |
Common questions about Semiconductor Design Engineer H-1B pay at Micron Technology
- How much does Micron Technology pay a Semiconductor Design Engineer on an H-1B?
- Micron Technology's median certified H-1B base salary for Semiconductor Design Engineer is $119k in FY2025, from 28 filings; the middle 50% of offers fall between $108k and $136k. Across all years the median is $119k.
- How many Semiconductor Design Engineer H-1B LCAs has Micron Technology filed?
- Micron Technology has 73 certified H-1B Labor Condition Applications for Semiconductor Design Engineer on record (FY2022–FY2026), 18 of them in FY2026. That is 1% of its 4,952 certified filings across all titles.
- Does Micron Technology pay Semiconductor Design Engineers above the market?
- Micron Technology's all-years median of $119k is in line with the $119k median for Semiconductor Design Engineer across all H-1B employers (90 certified filings).
- Where does Micron Technology hire H-1B Semiconductor Design Engineers?
- Micron Technology's Semiconductor Design Engineer LCAs name worksites mostly in Idaho, Texas, California; the top cities are Boise, ID, Richardson, TX, Atlanta, GA.
- Does a certified LCA mean an H-1B visa was approved?
- No. A Labor Condition Application (LCA) is the Department of Labor attestation an employer must have certified before filing an H-1B petition with USCIS. It records the job, worksite and offered wage, but not whether the petition was filed, selected in the lottery, or approved. Filing counts measure intent to sponsor, not headcount.
- What salary do these figures show?
- The base annual wage offered on the certified LCA, converted to a yearly amount. Bonus, equity, overtime and benefits are not included, so total compensation is typically higher. Figures are medians and percentiles over certified filings; wages above $5,000,000 a year are excluded as data-entry errors.
- What do prevailing-wage levels I–IV mean?
- The Department of Labor assigns each LCA an OES wage level from I (entry) to IV (fully competent) for the occupation and area. Under the FY2027 wage-weighted H-1B lottery rule, a higher level earns more selection entries, so an employer's level mix is a proxy for how senior its sponsored roles are.
Keep exploring
Calculate your H-1B lottery odds →orCheck out the insights →
Source: U.S. Department of Labor, Office of Foreign Labor Certification — certified LCA disclosure data through June 2026 (FY2022–FY2026). An LCA is not an approved visa; pay figures are base salary and exclude bonus and equity. Methodology →