ASIC Design Engineer H-1B salary at Marvell Semiconductor — 33 certified filings (FY2016–FY2020)
- 2
- Filings · FY2020
- $107k
- Median base · FY2020
- $107k–$115k
- Middle 50% · FY2020
- −39%
- vs market median · all years
Marvell Semiconductor filed 2 certified H-1B LCAs for ASIC Design Engineer in FY2020, with a median base salary of $107k and the middle 50% of offers between $107k and $115k. Across all years its $88k median is 39% below the $145k market median for ASIC Design Engineer. It has filed 33 ASIC Design Engineer LCAs since FY2016, most often in Santa Clara, CA.
How much does Marvell Semiconductor pay a ASIC Design Engineer?
Certified base salary for ASIC Design Engineer at Marvell Semiconductor by fiscal year: each box is the p25–p75 range, the heavy line the median, the whiskers reach p10–p90. $107k median in FY2020. Base pay only — hover a year for its figures.
Does Marvell Semiconductor pay ASIC Design Engineers above the market?
Marvell Semiconductor's all-years median against every employer's certified ASIC Design Engineer LCAs — 39% below the market. Same cleaned DOL title, same base-salary definition, so the two rows compare like for like.
| Base salary for this title | Filings | Median |
|---|---|---|
| Marvell Semiconductor | 33 | $88k |
| All employers · ASIC Design Engineer | 997 | $145k |
How has Marvell Semiconductor's ASIC Design Engineer hiring changed by year?
16 certified ASIC Design Engineer filings in FY2016 → 2 in FY2020. The change column is each year against the one before.
| Fiscal year | Filings | vs prior FY | Median base |
|---|---|---|---|
| FY2020 | 2 | 0% | $107k |
| FY2019 | 2 | +100% | $87k |
| FY2018 | 1 | −92% | $101k |
| FY2017 | 12 | −25% | $94k |
| FY2016 | 16 | — | $88k |
Which wage levels does Marvell Semiconductor file for ASIC Design Engineer?
DOL prevailing-wage levels I–IV approximate experience tiers (I = entry, IV = fully competent). 0% of Marvell Semiconductor's ASIC Design Engineer filings sit at Level III–IV. Higher levels earn more entries in the wage-weighted H-1B lottery.
Share of 2 ASIC Design Engineer filings with a wage level · all years
- Level II100.0%2
Where does Marvell Semiconductor hire H-1B ASIC Design Engineers?
Worksite states and cities on the certified filings for this title, all years, with the median base salary at each.
| State | Filings | Median base |
|---|---|---|
| California | 30 | $88k |
| Idaho | 2 | $83k |
| Colorado | 1 | $78k |
| City | Filings | Median base |
|---|---|---|
| Santa Clara, CA | 29 | $88k |
| Boise, ID | 2 | $83k |
| Aliso Viejo, CA | 1 | $86k |
| Longmont, CO | 1 | $78k |
Also filed as
Marvell Semiconductor's other sponsored titles, and the employers that file the most ASIC Design Engineer LCAs. All years.
Other titles at Marvell Semiconductor
| Job title | Filings | Median base |
|---|---|---|
| Staff Engineer | 78 | $130k |
| Senior Staff Engineer | 40 | $153k |
| Senior Engineer | 39 | $113k |
| Analog Ic Design Staff Engineer | 34 | $154k |
Top ASIC Design Engineer sponsors
| Employer | Filings | Median base |
|---|---|---|
| Apple | 845 | $149k |
| Fortinet | 13 | $137k |
| Spreadtrum Communications USA | 10 | $82k |
| Ambarella | 8 | $111k |
| Nvidia | 8 | $145k |
| Micron Technology | 7 | $123k |
| Space Exploration Technologies | 7 | $130k |
| Infinera | 7 | $107k |
| Scalable Systems Research Labs | 6 | $96k |
Common questions about ASIC Design Engineer H-1B pay at Marvell Semiconductor
- How much does Marvell Semiconductor pay a ASIC Design Engineer on an H-1B?
- Marvell Semiconductor's median certified H-1B base salary for ASIC Design Engineer is $107k in FY2020, from 2 filings; the middle 50% of offers fall between $107k and $115k. Across all years the median is $88k.
- How many ASIC Design Engineer H-1B LCAs has Marvell Semiconductor filed?
- Marvell Semiconductor has 33 certified H-1B Labor Condition Applications for ASIC Design Engineer on record (FY2016–FY2020), 2 of them in FY2020. That is 1% of its 2,247 certified filings across all titles.
- Does Marvell Semiconductor pay ASIC Design Engineers above the market?
- Marvell Semiconductor's all-years median of $88k is 39% below the $145k median for ASIC Design Engineer across all H-1B employers (997 certified filings).
- Where does Marvell Semiconductor hire H-1B ASIC Design Engineers?
- Marvell Semiconductor's ASIC Design Engineer LCAs name worksites mostly in California, Idaho, Colorado; the top cities are Santa Clara, CA, Boise, ID, Aliso Viejo, CA.
- Does a certified LCA mean an H-1B visa was approved?
- No. A Labor Condition Application (LCA) is the Department of Labor attestation an employer must have certified before filing an H-1B petition with USCIS. It records the job, worksite and offered wage, but not whether the petition was filed, selected in the lottery, or approved. Filing counts measure intent to sponsor, not headcount.
- What salary do these figures show?
- The base annual wage offered on the certified LCA, converted to a yearly amount. Bonus, equity, overtime and benefits are not included, so total compensation is typically higher. Figures are medians and percentiles over certified filings; wages above $5,000,000 a year are excluded as data-entry errors.
- What do prevailing-wage levels I–IV mean?
- The Department of Labor assigns each LCA an OES wage level from I (entry) to IV (fully competent) for the occupation and area. Under the FY2027 wage-weighted H-1B lottery rule, a higher level earns more selection entries, so an employer's level mix is a proxy for how senior its sponsored roles are.
Keep exploring
Calculate your H-1B lottery odds →orCheck out the insights →
Source: U.S. Department of Labor, Office of Foreign Labor Certification — certified LCA disclosure data through June 2026 (FY2016–FY2020). An LCA is not an approved visa; pay figures are base salary and exclude bonus and equity. Methodology →